A Direct 100 GHz Parametric CMOS Tripler

Abstract

The first direct anti-series CMOS tripler is described in this letter. MOS varactors are arranged in a back-to-back configuration free of the self-bias problem that prevents standard Schottky varactors from employing such an arrangement. Implemented in 130 nm CMOS, the circuit achieves a 28 dB conversion loss at 102 GHz with an output power of -20 dBm.