A Digitally-Assisted Electrothermal Frequency-Locked Loop in Standard CMOS

Abstract

This chapter describes an electrothermal frequency-locked loop (FLL) that is suitable for CMOS integration. An electrothermal FLL requires a narrow noise-bandwidth to limit the jitter resulting from the thermal noise of its electrothermal filter (ETF). This is rather challenging to implement in the analog domain, since the narrow bandwidth requires the realization of a large time constant. This chapter proposes a digitally-assisted FLL (DAFLL) architecture that mitigates the integration difficulties of previous FLLs. In the DAFLL, the narrow-band loop filter is realized in the digital domain. As such, it does not require off-chip analog components. Initially, the proposed system-level architecture will be introduced. Later, the design, implementation and characterization of the major building blocks will be covered. These include a phase digitizer realized by means of a phase-domain ΔΣ modulator (PDΔΣM), and a digitally-controlled oscillator (DCO).