A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL

Abstract

This paper presents a digital phase noise cancelling scheme for ring oscillator (RO)-based fractional-N ADPLL, which can suppress both in-band and out-of-band phase noise of RO. The scheme adopts a high-resolution time-to-digital convertor (TDC) to sample the rising edge timing errors between RO output and the reference signal (REF) and a matched digital-to-time convertor (DTC) to compensate these timing errors to align RO output with each rising edge of REF, eliminating the phase noise of RO output. To get accurate phase noise cancelling, it is essential to realize high resolution and good match between TDC and DTC. These two modules are implemented in 40nm CMOS with 2ps resolution and 8.34% mismatch. System-level simulation results show that, the in-band phase noise at 1 MHz offset can be cancelled by the level of 20 dB and the out-of-band phase noise at 10 MHz offset can be cancelled by 10 dB, with the 200 MHz reference signal.