A Digital ΣΔ Modulated Class-S Transmitter with Two-Step Up-conversion and Filter-less Front End

Abstract

A fully-digital Class-S transmitter implemented in 65-nm CMOS is proposed. In the filter-less digital front end (DFE) of the transmitter, a 40 MHz bandwidth time-interleaved (T-I) ΣΔ modulator operating up to 1.92 GHz sampling rate at center frequency of 480 MHz is performed. And two-step mixing technique is adopted to achieve the gigahertz carrier frequency at implementable operating frequency. The measured power consumption of the DFE is 13mW under a 1.2 V supply voltage when a 10 MHz LTE signal is applied and the carrier frequency of the transmitter is up to 2.4 GHz.