A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework

Abstract

Complex compute and communication SoCs in scaled CMOS process integrate synthesizable digital logic along with many analog/mixed-signal circuits such as PLLs and LDOs. While the digital logic blocks can be ported easily across process nodes, the analog/mixed-signal circuits demand custom manual re-design for physical layout, verification and optimization. Furthermore, fine-grain power management and noise isolation necessitate implementation of a large number (>50) of independent voltage domains on die. The manual layout effort and time for such a large variety of critical analog/mixed-signal circuit blocks becomes increasingly unaffordable in practice. Also, physical layout requirements like common-centroid and inter-digitization, and routing requirements such as matching differential nets, minimizing interconnect parasitics of critical leaf cells like differential pairs, current mirrors, resistors and capacitor arrays, necessitate multiple iterations with post-layout verifications, thus significantly impacting overall design time and time-to-market. Furthermore, availability of high-quality mask-design engineers can pose a major bottleneck to timely completion of the design, especially for the increasingly complex layout design rules in scaled process nodes. Multiple EDA frameworks, such as ALIGN [1], BAG [2] and MAGICAL [3] were reported to generate analog layouts for improving design productivity of analog circuits in scaled CMOS. However, there is still a need for a methodology that can accommodate the varying needs of analog circuits and generate high quality layout while leveraging automated placement and/or routing. In this paper, we present an analog layout generator (ALG) methodology based digital LDO (DLDO) with a self-triggered binary search windowed flash ADC in 22nm CMOS (Fig. 1) to maximize the productivity of implementing analog circuit blocks in scaled CMOS process, thus significantly improving the overall design time & effort, as well as time-to-market for complex SoCs. A self-triggered binary search mechanism with a delay-based architecture is proposed to reduce the exponentially growing kickback noise and energy consumption of a traditional flash ADC down to the level of a SAR ADC while maintaining its high speed feature.