Abstract
AbstractThis paper describes a new algorithm of self-organizing relationship (SOR) network for an efficient digital hardware implementation and also presents its digital hardware architecture. In SOR network, the weighted average of fuzzy inference takes heavy calculation cost. To cope with this problem, we propose a fast calculation algorithm for the weighted average using only active units. We also propose a new generating technique of membership function by representing its width on power-of-two, which suits well with the digital hardware bit-shift process. The proposed algorithm is implemented on FPGA with massively parallel architecture. The experimental result shows that the proposed SOR network architecture has a good approximation ability of nonlinear functions.
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