A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique

Abstract

A 6-bit time-to-digital converter that achieves mismatch free operation by using a single delay cell and sampling flip-flop is presented. The proposed TDC was integrated in a digital fractional-N PLL fabricated in a 32-nm digital SoC CMOS process for WiFi/WiMax radios. The TDC consumes 3 mW from a 1.05-V supply and occupies an area of 0.004 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A digital frequency-locked loop is used to track and correct for PVT variations in the TDC and no additional linearization or mismatch calibrations are required. The DPLL uses a 20-bit high dynamic range DAC to drive a VCO in order to effectively realize a DCO with 100-Hz frequency resolution. The 2.5-GHz WiFi band LO output is generated from a 40-MHz reference with an integrated phase noise of - 35 dBc (10 kHz to 10 MHz) while consuming 21 mW . The worst case spur in the LO output is below - 50 dBc without requiring TDC mismatch and linearity calibration.