A Digital CMOS Silicon Photomultiplier Using Perimeter Gated Single Photon Avalanche Diodes With Asynchronous AER Readout

Abstract

This paper presents a new architecture for a perimeter gated single photon avalanche diodes (PGSPADs) based CMOS digital silicon photomultiplier (SiPM) with fully digital asynchronous address event representation (AER) readout. A PGSPAD is a single photon avalanche diode with an additional polysilicon gate and mitigates the perimeter edge breakdown, modulates the noise floor, dynamic range, and sensitivity of the device. Spatial and temporal data compression techniques in the SiPM pixel improve dead time, and reduce electronics. Fill factor is improved using a compact, low power analog counter. The dead time improves by 25% with temporal compression improving by a factor of 10 for the pixel microcell. A $4\times 4$ pixel array in a standard $0.5~\mu \text{m}$ CMOS process is fully characterized for the dark counts as function of gate and excess bias as well as varying optical intensity. The array-level dynamic range is 142 dB.