Abstract
Logic reasoning represents a new class of artificial intelligence. This work presents the first hardware implementation of the Differentiable Neural Computer accelerator based on brain inspired “working memory” concept for reasoning tasks. A special near-memory computing architecture is developed achieving high scalability and over 90% utilization of computing resources. Sparsity based enhancements such as zero skipping, data compression are applied with 30% speedup of the computing latency. A 65nm test chip was fabricated with demonstrations on a variety of logic reasoning tasks showing 700X and 46X speedup compared with CPU and GPU and up to 1.28TOPS/W power efficiency.
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