Abstract

A high-voltage multiplexer fabricated with both junction-isolated ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">JI</tex> ) and dielectrically isolated ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DI</tex> ) D/CMOS process technologies is described in this paper. This eight-channel multiplexer is capable of switching a ± 50-V analog-signal range from a ± 60-V power supply. The switches exhibit less than 50 Ω of on-resistance and are capable of peak currents in excess of 0.5 A. An off-switch current model incorporating junction area and lifetime-dependent lateral DMOS drain-to-body and drain-to-substrate leakages is described. Elimination of the drain-to-substrate diode with dielectric isolation results in a factor of 15 reduction in leakage at 25°C and a factor of 10 improvement at 125°C, which agrees well with the model developed. Results show that the generation current from the space-charge region dominates device leakage at room temperature, while diffusion current from the neutral regions is predominant at elevated temperatures. In high-voltage testers, dielectrically isolated multiplexers offer the low leakage and high accuracy required by critical channels where less costly junction-isolated devices will not suffice.

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