Abstract
Channel loss dominated the performance of the high speed I/O signals. The loss budget affects the ratio of cost and price directly. Owing to the above reasons, the exact correction of the de-embedded result can make this ratio more readable for the platform design guide. Due to the systematization, an algorithm is presented, which comprises a 2X-thru de-embedding method and an empirical mode decomposition (EMD) in this article. This 2X-thru de-embedding system includes a mix-mode calculation for differential mode S-parameters extraction, a time-domain channel characterization (TCC) for the midpoint of time sifting, and a T-matrix cascading elimination for DUT extraction. The curve fitting method consists of an EMD or an ensemble empirical mode decomposition (EEMD) algorithm. This EMD/EEMD techniques have been applied for the elimination of ripple in the measure S 21 of transmission line with small impedance mismatches. This work also does the correction for SMA and D-probe measurement fit by EMD and EEMD algorithm. This systematized topology can propose a criterion for a commercially printed circuit board (PCB) system and can also extend to the high-speed PCB system such as PCIe-5 and 6.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.