A Design of Small Area, 0.95 mW, 612⁻1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications.

Sungjin Kim,Dong Lee,Behnam Samadpoor Rikan,Kang-Yoon Lee,Youngoo Yang,Sang-Sun Yoo,Chanho Kim,Minjae Lee,Dong-Gyu Kim,Younggun Pu,Keumcheol Hwang

doi:10.3390/s18061777

Abstract

This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver places a burden on this system because of the additional area and power consumption that is required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled Frequency Locked Loop (FLL). This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612–1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is −108 dBc/Hz at a 1 MHz offset.

Highlights

The Internet of Things (IoT) has been applied to many applications, such as sensor networks and wearable devices
We propose an Injection-Locked Frequency Multiplier (ILFM) with small chip area and low power consumption using
The proposed design is fabricated in a 0.18 μm CMOS process and the layout size of the entire ILFM including Ring Oscillator, Injection Generator and Frequency Locked Loop (FLL) is 0.54 mm × 0.12 mm

Summary

Introduction

The Internet of Things (IoT) has been applied to many applications, such as sensor networks and wearable devices. In these applications, low power consumption and small chip area are required to increase battery life and reduce system cost. Low-Intermediate Frequency (IF) receiver architectures have become popular for low-power applications. These structures offer advantages over Zero-IF architectures in terms of the DC-Offset calibration and flicker noise [1]. Analog parameter variations in the local oscillators, mixer and filters result in gain and phase errors between I/Q paths Due to these errors, image leaks into the signal band during the down-conversion process. The low-IF receiver has a low image rejection ratio (IRR), as shown in Figure 1 [2]

Methods

Results

Conclusion