Abstract

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (VCM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is $45~\mu \text{W}$ when operated at 1 V power supply.

Highlights

  • Nowadays Internet of Things (IoT) are applicable for many applications such as sensor networks, wearable devices and health care [1]

  • As dynamic latch architecture can introduce large input referred offset, which is not suitable for medium and high resolution Analog-to-digital converters (ADCs), we have reduced its effects by increasing the sizes of the input transistors in differential pair [29]–[32]

  • This paper presents a 10-bit low power asynchronous successive approximation register (SAR) ADC for IEEE 802.15.1 IoT sensor based applications

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Summary

INTRODUCTION

Nowadays Internet of Things (IoT) are applicable for many applications such as sensor networks, wearable devices and health care [1]. D. Verma et al.: Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC. A tri level switching scheme named as reverse VCM based scheme which maintains good linearity without any driving and accuracy requirements on VCM is represented in [6], and charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth is shown in [7]. This paper represents the optimization of power efficiency and area along with the speed of SAR ADC.

ASYNCHRONOUS SAR ADC ARCHITECTURE
DYNAMIC LATCH COMPARATOR WITH APC
ASYNCHRONOUS SAR LOGIC
MEASUREMENT RESULTS
CONCLUSION
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