A design of 14-bits ΣΔ ADC and DAC for CODEC applications in 0.18 μm CMOS process

Abstract

This paper presents a σ-δ modulation ADC (analog-to-digital converter) and DAC (digital-to-analog converter) for CODEC applications using 0.18 μm CMOS process. In the ADC parts, two σ-δ modulators with 84 dB SNR are designed for the stereo applications, and their outputs are merged at the digital domain before decimation filter. Digital decimation filter is integrated with the analog σ-δ modulators for the full ADC operation. In the DAC parts, the digital data is first processed at the interpolator filters, and modulated by the following σ-δ modulators. To reduce the mismatch effect of the following DAC, the dynamic element matching method is proposed in this paper. It is designed with 0.18 μm CMOS process. The simulated SNR is about 100 dB. and the power consumption is 40 mA.