Abstract

This paper presents a 10-b ADC designed in a 0.18-μm CMOS technology. The ADC achieves 10-b resolution by using the cascaded folding technique in both the fine and coarse converters. Folding stages are pipelined to improve the settling time. As a result, this ADC can achieve the sampling rate up to 100MS/s. Moreover, instead of using a costly single track-and-hold circuit, a distributed track-and-hold circuit is used to reduce the chip area and the power consumption. This also allows utilizing the open-loop architecture of the folding technique, thus improving the performance of the system. The simulation results show that with a 49 MHz sine-wave input, the ADC consumes 66 mW and the effective number of bit (ENOB) is 9.28-b. Taking into account of process variations by using a Monte Carlo simulation, the DNL varies from ±0.45LSB to ±0.25LSB. The layout of the ADC occupies 1.2 mm2 die area.

Highlights

  • The development of CMOS technology has led to a dramatic growth of high performance digital signal processing systems

  • Because of its parallel architecture, flash analog-to-digital converters (ADCs) can be the fastest type of ADCs [1,2,3]

  • The open-loop architecture of flash ADC is attractive for high speed, while the multi-step architecture of two-step and pipelined ADCs are necessary to improve resolution

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Summary

INTRODUCTION

The development of CMOS technology has led to a dramatic growth of high performance digital signal processing systems. Many new folding architectures have been proposed to improve speed and resolution while achieving lower hardware complexity and power dissipation. This non-linear effect poses some serious problems when designing a folding ADC. This method solves the linearity requirement of folding signals, it leads to high power consumption and occupies large chip area. Active interpolating uses differential pairs to create interpolating signals This increases the gain of the output signal and has the best linearity, power dissipation and hardware complexity will be higher than resistive interpolating.

Design of ADC
CONCLUSION
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