A design approach for analog neuro/fuzzy systems in CMOS digital technologies

Abstract

This paper presents adaptive circuit blocks and related learning algorithms to design neuro/fuzzy inference systems using analog integrated circuits in CMOS, standard VLSI technologies. The proposed circuit building blocks are arranged in an architecture composed of five layers: fuzzification, T-norm, normalization, consequent, and output. Inference is performed using Takagi and Sugeno’s if-then rules, particularly where the rule’s output only contains a constant term — a singleton. The proposed learning scheme uses weight perturbation for the fuzzification layer and outstar for the output layer. A three-input, four-rule controller has been designed for demonstration purposes in 1.6 μm CMOS single-poly, double-metal technology, and obtains operation speed in the range of 5 MFlips with around 1% systematic errors.