A delamination study on metallization stacks of power semiconductors

Abstract

The requirements on the interfacial strength of metallization stacks in modern power semiconductor devices are becoming more and more demanding. Delamination is a common failure mode found in such microelectronic components. Residual stresses, originating during deposition commonly occur in these metallization film stacks. It has been demonstrated that these residual stresses can significantly change the driving force for interfacial delamination. The four-point bending (4PB) test is an appropriate method to quantitatively measure the delamination resistance and energy release rate. In this study the influence of Cu metallization thickness and residual stresses on the adhesion strength of SiOx/SiNx/TiW/Cu film stacks on Silicon were investigated. In addition to detailed microstructural and chemical analysis of the film stacks and its interfaces, we used X-ray diffraction (XRD) residual stress measurements as well as wafer bow methods to estimate the stress in the Cu films and the film stack respectively. Static 4PB technique was used in order to determine the interfacial adhesion properties of the samples. In addition Finite Element Analysis was performed to verify analytical calculations. Delamination occurred always in the interface between Si and the amorphous SiOx layer. This can be explained by the loading conditions imposed by the 4PB set-up and the selected sample geometry.