A Decision Tree Synthesis Flow for Precise and Approximate Circuits

Abstract

Logic and physical synthesis are getting more integrated, aiming to obtain an optimized circuit in terms of delay, power, and area. However, the current traditional tools used in Boolean logic optimization, in some cases, require a high runtime to afford an efficient minimization. Decision Tree approaches are capable of providing efficient and fast solutions for logic optimization. This work presents a logic optimization flow based on Decision Trees for approximate circuits and evaluates its efficiency in area, delay, and accuracy considering F PGA and ASIC synthesis. Compared to commercial tools, the proposed flow reduces up to 58% area and 38% power on ASIC synthesis and up to 77% the resources utilization on FPGA synthesis, with a slight reduction in accuracy on a few outputs.