A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL

Abstract

This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation ($$F_{\max }$$) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 $$\upmu $$W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 $$\upmu {\text {m}}^2$$.