A dc approach for analog fault dictionary determination

Abstract

Efficient solution of dc node voltages for nonlinear analog electronic circuits has been demonstrated by computer-aided circuit analysis programs such as SYSCAP II [1] (System of Circuit Analysis programs) for the nominal case and for inserted faults. In addition dc node voltage postprocessing techniques [2] have been developed to determine required input stimuli and the minimum number of test points that will achieve detection of predetermined faults to a prescribed level, and isolation to a prescribed number of devices [3]. Thewe techniques offer a systematic approach for pretest generation of analog fault dictionaries. The effectiveness of this approach depends upon inclusion of a sufficiently high percentage of potential field failures in the fault dictionary, and upon implementation of the inherent testability design features of the dc approach, i.e, to have specified adequate test stimuli and to have indicated the appropriate nodes/test points for accessibility. In this paper we examine actual field failure statistics and identify which of these field failures could realistically have been predetermined and modeled by the dc approach. Finally an estimate is made of the percent of actual field failures that can be detected and isolated by the dc approach.