A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core

Abstract

Cross-coupled differential pairs implement an even-order active frequency multiplier in 90 nm SiGe-BiCMOS. The multiplier core uses asymmetric biasing to realize an even-order transfer function. Wideband (WB) and narrowband doublers built around the active core are proposed, and their relative performance is compared from simulation. Measurement of a WB prototype consisting of the doubler, active load with feedback regulation of bias, and 50 $\Omega$ input and output buffers validates the circuit concepts. Conversion gain (CG) for the WB doubler peaks at low frequency (e.g., 12 dB at 10 GHz) and rolls off to 0 dB at 100 GHz. For 25 GHz output, significant spurs are: $-$ 25 dBc at 12.5 GHz (input tone) and $-$ 28 dBc at 50 GHz (4th harmonic). The 0.37 mm $^{2}$ WB testchip consumes 55.5 mA from a 4.5 V supply.