Abstract

An analog-to-digital conversion (ADC) scheme based on asynchronous ΔΣ modulation and time-to-digital conversion is presented. An asynchronous ΔΣ modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications.

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