A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication

Abstract

A novel pole-tuning technique with T-type network for interstage bandwidth extension is proposed in this paper. By exploiting the proposed technique in interstage of amplifiers, the transfer function of each stage exhibits two dominant poles, achieving a flat gain–frequency response over an ultrawide bandwidth. For verification, a four-stage amplifier based on the pole-tuning technique with T-type network has been designed and implemented in a 65-nm bulk CMOS technology. The fabricated prototype achieves a peak gain of 9.5 dB at 122 GHz with a 3-dB bandwidth of more than 26 GHz and a fractional bandwidth of larger than 21.3%, while consuming a dc power of 62 mW. At the operating frequency of 125 GHz, the saturation output power and the output P1 dB are 8.6 and 4.6 dBm, respectively. The chip occupies a small silicon area of 0.27 mm2 including all testing pads with a core size of only 0.105 mm2. The proposed amplifier is suitable for short-distance data center communication as one of the key building blocks.