A customized and reconfigurable VLIW-based packet classifier on ρ-VEX

Abstract

The bandwidth growth of networks increased almost exponentially in the recent years and is expected to continue so for years to come. This has been fuelled by emerging new technologies that are capable of achieving higher bandwidths. Consequently, new applications are being developed that take advantage of the new capabilities. These complex applications and heavier traffic have emerged demands on more powerful devices. Furthermore, due to dynamic nature of network traffic, totally scalable methods for packet processing and implementation platforms that are able to cope with this dynamicity are needed. Field-Programmable Gate Arrays (FPGAs) are efficient candidates as they contain hardware programmable logic units that can be reconfigured based on the application requirements. ρ-VEX is a reconfigurable soft-core Very Long Instruction Word (VLIW) processor on an FPGA and it is able to use the inherit Instruction Level Parallelism (ILP) of applications. ρ-VEX has all the requirements of processing network applications. For the purpose of scalability and economical reasonability, in this paper, an implementation of CRC called one-clock CRC (OC-CRC) as a customized instruction in ρ-VEX is presented. Using this customization, one of packet classification algorithms that have taken advantage of Bloom filter e.g. tuple pruning using Bloom filter is implemented. CRC is selected as a custom instruction because of its importance in Bloom filter as hashing function and error detection in the most of the layer of common protocol stacks. The results show the huge performance gap between General Purpose (GPP) processors and our customized ρ-VEX such that our customized ρ-VEX provided on average approximately 8× speedup.