A current-reuse Class-C LC-VCO with an adaptive bias scheme

Abstract

This paper proposes a low-power currentreuse complementary differential LC-VCO which is composed of a pair of NMOS and PMOS transistors with an adaptive bias scheme for both transistors to ensure its robust startup and achieve maximum swing in Class-C operation. The proposed VCO has been implemented in a standard 0.18μm CMOS technology, which oscillates at the carrier frequency of 4.6 GHz. The measured phase noise is -139.5dBc/Hz at 10 MHz offset while drawing a current consumption of 1.6 mA from 1.5 V supply. The Figure of Merit is -189.1 dBc/Hz. To the author's best knowledge, this is the first class-C current-reuse VCO with an adaptive bias scheme.