Abstract

In this paper, we present a continuous-time current-mode $\Sigma\triangle$ modulator (CT C-SDM) with finite impulse response (FIR) feedback to increase clock jitter robustness while preserving the anti-aliasing filtering (AAF) property of a CT modulator. The modulator also features a newly proposed DC servo loop (DSL) that extends the modulator’s dynamic range in applications with a large DC bias current. This improvement breaks the intrinsic tradeoff between dynamic range and quantization noise floor of C-SDM for applications which require the digitization of AC currents in the presence of strong DC bias currents. The proposed modulator architecture has been manufactured in 180nm CMOS, and consumes 64mW from a 3. 3V supply. The chip’s measured peak SNR and SNDR are 77 dB and 76.8 dB, respectively. The modulator can accommodate AC signal currents up to 137$\mu \mathrm{A}_{\mathrm{p}\mathrm{p}}$ and features an integrated noise of 6.9 n$\mathrm{A}_{\mathrm{r}\mathrm{m}\mathrm{s}}$ over a 200 kHz bandwidth, corresponding to a noise floor of 15 pA/$\sqrt{\mathrm{H}\mathrm{z}}$. An off-chip implementation of the proposed DSL verifies its positive effect on the modulator’s dynamic range (DR) without deteriorating the modulator’s noise performance and/or stability properties.

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