A current-draining folded up-conversion mixer and pre-amplifier stage in a CMOS technology for IEEE 802.11a WPAN applications

Abstract

This paper describes a 3.5-GHz up-conversion mixer core utilized in a two step transmitter architecture in compliant with IEEE 802.11a WPAN application. The design is based on current-draining folded architecture. The main advantage of the introduced mixer topology is: high linearity and moderate conversion power gain. The mixer is designed in a 0.18-/spl mu/m CMOS technology, operating from 1.8-V power supply. The integrated up-converter and preamplifier consumes 5 mA and 22 mA of current respectively from 1.8-V supply and shows 4.73-dBm OIP3 (-1.74-dBm IIP3) and -9.41-dBm P1 dB with 5.65 dBm of conversion power gain.