A Cube-based Approach to Reachability Analysis

Abstract

Reachability analysis is an important step in formal verification, synthesis, and testing of sequential circuits. Symbolic algorithms that represent state sets and perform image computation by binary decision diagram (BDD) have been developed for more than one decade. Those symbolic methods are timeframe-based, i.e., performing image computation on the whole state set one timeframe after another timeframe. However, the image computation operation on large sequential circuits becomes more intractable due to explosive expansion of BDD size. Thus, computing the entire reachable state set in each timeframe becomes impractical in the reachability analysis. In this paper, we propose a novel cube-based algorithm that does not compute the complete reachable state set of each timeframe at a time. The cube-based algorithm traverses the state space in a divide-and-conquer manner to maximize the number of reached states with limited computation resources. This approach performs partial small image computations iteratively instead of one complete but huge image computation. As a result, the computation complexity of each iteration would be smaller, so does the CPU time and memory usage. Therefore, the reaching process would not get stuck in a certain timeframe in which image is too complex to be computed. As comparing the results with VIS, this approach could reach more states within the same CPU time and use less memory.