A CT ΔΣ modulator using 4-bit asynchronous SAR quantizer and MPDWA DEM

Abstract

The current paper aims at presenting a low-power second-order input-feedforward continuous-time (CT) ΔΣ modulator for audio applications. It uses a 4-bit asynchronous successive approximation register (SAR) quantizer which is more power efficient than the usual flash converter. Furthermore, in order for the proposed modulator to reduce the noise stemming from the component mismatches of the feedback digital-to-analog converter (DAC), it applies a modified partitioned data weighted averaging (MPDWA) dynamic element matching (DEM) so as to solve the DWA DEM-in band-tone problem. Despite the implementation of MPDWA, no further delay caused in the ΔΣ feedback loop compared to the conventional DWA. The implementation of the above-mentioned DEM in the modulator and required reforms have led to a new design with better performance and favorable figure of merit (FOM) value. The designed modulator which is simulated using 0.18 µm CMOS technology, achieves 84.17 dB SNDR for 20 kHz signal bandwidth and dissipates 54 µW while its FOM is obtained about 143 fJ/conv.-step.