A CSA-Based Architecture of Vedic Multiplier for Complex Multiplication

Abstract

The critical process in modern digital signal processing systems is complex multiplication. The speed and complexity of overall system depend upon complex multipliers. In this paper, a multi-operand carry-save adder (CSA)-based Vedic multiplier for complex multiplication is proposed. The proposed Vedic multiplier is based on Urdhva Tiryakbhyam Sutra of Vedic mathematics. For the improvement in the performance of the proposed Vedic multiplier architecture, CSA and Binary to Excess-1 code converters are used. Proposed \(32 \times 32\) bit Vedic multiplier, \(64 \times 64\) bit Vedic multiplier and complex multiplier architectures are implemented using VHDL in Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with the conventional booth and array multiplier-based architectures, which shows that the proposed scheme provides improved delay, low hardware (LUTs) and low complexity. Due to higher bit multiplication rate and low power dissipation, the proposed architecture is useful for modern wireless communication applications.