A cost-effective programmable SoC for network security using Xilinx Spartan 3AN FPGA

Abstract

Purpose – With the rapid development in wired and wireless networks, the demand for network security system is rising rapidly due to more and more new applications introduced. The main factors that rate the encryption algorithms are its ability to secure and protect data against attacks, its speed and efficiency. In this paper, a reconfigurable network security design using multi-mode data encryption standard (DES) algorithm has been implemented with low complexity and low cost, which will also reduce the speed. The paper aims to discuss these issues. Design/methodology/approach – The design can be easily reconfigured to 3DES (triple DES) which is more secure and more powerful in encryption and decryption, as one of the trick in designing 3DES is to reuse three instances of DES. The design can be used for wired and wireless network applications, and it has been described using VHDL and implemented in a reconfigurable Programmable System-on-Chip (PSoC). The hardware implementation has targeted Xilinx Spartan XC3S700-AN FPGA device. Findings – The main idea of reducing the complexity for the hardware implementation is by optimizing the number of logic gates and LUTs of the design. The number of logic gates can be decreased by changing the way of writing the VHDL code and by optimizing the size of the chip. Originality/value – The design has been tested in simulation and hardware levels, and the simulation results and performance are discussed.