A cost-effective approach for efficient time-sharing of reconfigurable architectures

Abstract

Reconfigurable computing is rapidly establishing itself as a major discipline, involving the use of reconfigurable devices for computing purposes. This paper proposes the ORRes approach for a time-sharing of reconfigurable resources. We investigate the overlay architecture at the hardware layer to ensure the bitstream compatibility between heterogeneous FPGAs. Two novel overlay features are introduced: i) a snapshot register to monitor the execution at run-time, and ii) a pre-loading to minimize the reconfiguration time overhead. We also propose accurate cost models of all components of the scheduling scheme. The proposed approach is evaluated on the APF6-SP SoC+FPGA platform. A 90% of models' preciseness is achieved, and costs 300x less in reconfiguration time compared to the literature.