Abstract
This paper presents the implementation of back-end design and optimization for Sinusoidal Pulse Width Modulation (SPWM) generator using Silterra 0.18 μm technology and it is based on CORDIC algorithm. The SPWM technique is used to control switches such as Insulated Gate Bipolar Transistor (IGBT) in major power electronics appliances such as the Single Phase Matrix Converter (SPMC). Synopsys tool is used to synthesize the Resistor Transistor Level (RTL) netlist written in Verilog Hardware Description language (HDL) and also to design and optimize the back-end layout design. The use of Coordinate Rotation Digital Computer (CORDIC) algorithm in the design of the SPWM generator, results in an area-efficient architecture for effective design implementing Silterra's 0.18 μm CMOS technology.
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