A Conformal Oxide Liner for Through Silicon Vias by Pulsed SA-CVD Deposition

Abstract

In 3D integration technology, TSVs (Through Silicon Via) are used to electrically interconnect stacked chips. The preferred isolation process is SA-CVD O3/TEOS based oxide because it is conformal and has a high deposition rate at low temperature. A drawback is a high TSV density dependency that leads to a non-uniform liner thickness across the chip and along the whole wafer. Using a pulsed flow 400{degree sign}C O3/TEOS process, we obtained a superior result in terms of conformality and structure density dependency for via's with aspect ratio 10 (2x20 and 5x50μm). The process strongly outperforms standard processes without pulsing.