Abstract
AbstractEarlier, the authors proposed a processing scheme for expansion of the MR/MMR code to improve the performance close to the limit of the method. This paper proposes the processing scheme for MR/MMR encoding (compression) which can suitably be combined with the previously proposed expansion processing scheme. The two schemes are combined to form a CODEC, which is implemented as an LSI;, and the result of evaluation is reported here. This kind of LSI will frequently be used in image retrieval‐type applications, and it is important to reduce the time for expansion processing.In this study, the hardware needed in the proposed high‐performance expansion scheme is determined first and then the functions needed in the compression are mapped on the architecture. The length of the machine cycle is optimized from the viewpoint of expansion. When the delay in the compression circuit exceeds the machine cycle time, the function is divided into two cycles.It is shown that the priority order of pass mode and V mode recommended by T.4/T.6 of CCITT desirably should be reversed from the viewpoint of design, in the case of compression processing. The effect of this reversal is examined. Based on those ideas, CODEC is designed and constructed. It is verified that the functions and performances are realized as are designed. The processing time is mostly proportional to the amount of images. The image data flow almost at a constant rate, which is convenient in the design of the pipeline structure.
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