A concept of gate oxide lifetime limited by "B-mode" stress induced leakage currents in direct tunneling regime

Abstract

To realize further advances in MOS ULSIs, thin gate oxides in the direct tunneling regime (<3 nm) are strongly required. In this regime, the most important issue is the soft breakdown (SBD) (Depas et al., 1996) which induces the stress induced leakage current (SILC) (Okada et al., 1994 and 1998; Okada and Kawasaki, 1995; Okada, 1997). Although Weir et al. (1997) reported that the SBD induces no significant degradation to a device, Wu et al. (1998) have recently reported that the oxide breakdown immediately leads to device failure for submicron short-channel-length devices, regardless of the SBD or the hard breakdown (HBD). These reports raise controversy on how to define the oxide lifetime in this regime. Needless to say, this problem also influences on the scaling limit of silicon dioxides as the gate dielectrics. This must be discussed from the perspective of the following two aspects: (i) oxide lifetime (reliability) (Stathis and DiMaria, 1998) and (ii) chip-level off-leakage current (standby power) due to the direct tunneling current (Lo et al., 1997; Timp et al, 1998). In this paper, we studied the degradation behaviour of 2.4 nm-thick thermal oxides before and after SBD. It was revealed that the limiting factor of the oxide lifetime is no longer the SBD nor HBD but the B-mode SILC in plural transistors induced by plural SBD.