A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Abstract

Abstract IIn this paper, two substrate optimization approaches of triple stacked Nanosheet FET (SNSHFET), namely optimization of buried oxide and selective deposition of punch through stopper (PTS) substrate, have been examined and simulations have been carried out using Technology Computer-Aided (TCAD) software. A comprehensive study of leakage current and key electrical characteristics (I¬ON, VT, SS, DIBL) have also been extracted based on variation in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. GIDL current also increases with increased doping of the source and drain. Also, the impact of ultra-thin body substrate in SNSHFET is studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in Inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed at the channel-drain and gate-substrate overlap region for understanding the physical insights of leakage current in the SNSHFET. This work also answers the dependency of GIDL current on the gate and drain voltage supply respectively. In addition to that, how GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. The 3 nm-based SNSHFET is designed and its electrical and GIDL characteristics are compared with novel devices like Forksheet FET and Complementary FET.