A Comprehensive Study for Specialized Silicon-on-Insulator Wafers

Abstract

The relentless advancement and trends on thinner packages have become the focus in the semiconductor manufacturing industry. The requirement of thinner packages also demands a thinner vertical structure of the semiconductor electronic design. As a major contributor on the vertical structure of the electronic package, die or wafer is also essential to go thinner. As the wafer becomes thinner, various problems may occur during transport and even the backgrinding process itself.
 Wafer warpage is one of the main concerns during the wafer backgrinding process. Insufficient vacuum may cause non-planar wafer in contact with the chuck table that may result to poor grinding and broken wafer. Wafer backgrinding stress and backgrinding tape tension also contribute to the effect on wafer warpage. Challenges exist in processing different silicon wafer technology, particularly the silicon-on-insulator (SOI) technology. Evaluating the effect of backgrinding tape selection and vacuum efficiency to eliminate such warpage is presented in this paper.