A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM

Abstract

The spin-transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology with several distinctive advantages such as nonvolatility, high density, scalability, and almost unlimited endurance. It is, therefore, seen as a promising candidate to replace conventional on-chip memory technologies. However, as the technology scales, yield loss due to extreme parametric variations is becoming increasingly important for STT-MRAM because of its higher sensitivity to process variation as compared to CMOS memories. In addition, the parametric variations in STT-MRAM exacerbate its stochastic switching behavior, leading to both test time fails and reliability failures in the field. Since an STT-MRAM memory array consists of both CMOS and magnetic components, the system-level failures in STT-MRAM depend on variations in both these components. In this paper, we model the system-level parametric failures of STT-MRAM considering the spatial correlation among bit cells as well as the impact of peripheral components. The proposed approach provides realistic fault distribution maps and equips the designer to investigate the efficacy of different combinations of defect tolerance techniques for an effective design-for-yield exploration. The results show that the fault distribution and yield depend on the correlation coefficient and the temperature, which, in turn, determine the correct choice of defect tolerance scheme to be adopted to mitigate them to improve the yield.