A comprehensive analysis of the effect of finite amplifier bandwidth and excess loop delay in continuous-time sigma–delta modulators

Abstract

A comprehensive study of the impact of the finite gain-bandwidth product (GBW) in amplifiers and the excess loop delay on CT ΣΔ modulators has been carried out in this paper. Variations in the modulator coefficients have been included too. Considering a second order modulator, our study was based on the dependence of the NTF poles and zeroes locus in the z-plane on these two non-ideal effects from both an analytical and a computer simulation approach. The corresponding STFs were also analytically evaluated. The theoretical and the simulated results have been compared with the experimental results obtained from a test-chip recently designed and implemented. Amplifiers were modeled according to a single-pole transfer function. Using the modified Z-transform method the dependence of the NTF poles and zeroes locus in the z-plane on the finite GBW and on excess loop delay was obtained when the DAC pulse end occurs in the current (“early”) or in the following (“late”) clock cycle. Once the theoretical analysis was validated, NTF poles and zeroes loci were evaluated as a function of the two non-ideal effects considered separately or combined. In each case, the order of the modulator loop filter was discussed. The finite GBW effect can be compensated including an intentional “early” DAC pulse. This pulse can be implemented in the modulator by changing the sampling instant in the embedded ADC with respect to the instant DACs are enabled by using a simple delay circuit for the ADC clock. Thus, the modulator power consumption can be significantly reduced.