Abstract
This paper presents a systematic analysis of breakdown mechanisms in silicon carbide MOSFET and JFET. For the MOSFET, the trench technology has been selected. The JFET structure is very similar to that having the distinctive feature of a buffer layer grown on the top of the drift region. Both devices are designed for 1.2 kV and were simulated and optimised using MEDICI and ISE TCAD software packages. This study indicates that the gate oxide breakdown puts a strong limitation on the electrical performance of the SiC trench MOSFET. Drawbacks encountered in SiC trench MOSFET, such as gate oxide breakdown, low channel mobility and the tight trade-off between the punch-through premature breakdown and the threshold voltage in the channel can be eliminated by using the SiC JFET.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
