A compare-and-select error tolerant scheme for nonvolatile processors

Abstract

This paper presents a compare-and-select (CaS) error tolerant scheme for nonvolatile processors (NVPs). Nonvolatile flip-flops (NVFFs), used in NVPs suffer from the faults caused by nonvolatile devices. Conventional error tolerant methods are designed for centralized memory macros and are inefficient for distributed NVFFs. In our CaS scheme, we use the read-write-read-compare strategy to get the error map of NVFFs and find out the NVFF bits with faults. Then the fully functional NVFF bits are selected to store data and the bits with faults are discarded. The advantage of our method is that it provides more redundancy with equal protecting bits, which is more efficient for distributed NVFFs. Experiment results show that with a bit fault rate of higher than 1% in NVFFs, in which case conventional ECCs nearly fail, the CaS scheme can provide the NVP with more than 99% fully function rate.