Abstract
To examine the dynamic nature of body-tied-to-gate (BTG) partially depleted SOI MOSFETs, CMOS inverter circuits (nine-stage ring oscillators and 50-stage chains) are simulated with SOISPICE, accounting for the BTG distributed body resistance. Due to the physical nature of the UFSOI model in SOISPICE, both the static and dynamic characteristics of the BTG device, contrasted to floating-body (FB) and body-tied-to-source (BTS) SOI MOSFETs, are faithfully revealed. Results give insight on previously measured, yet inadequately explained, dynamic behavior of the BTG device. Further, problematic hysteretic behavior associated with the dynamic operation of the device with realistic body sheet resistance is described, suggesting design constraints on the maximum device width. Finally, a performance assessment of the BTG device configuration in ultra-low-power CMOS digital applications is offered and compared with FB and BTS, indicating that the optimal configuration is in fact application-specific.
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