A Comparative Analysis of HPL-PD and MIPS Architectures by Using Integrated Approach for IS and RA for Exploiting ILP

Abstract

In this article, the authors have proposed an integrated algorithm for instruction scheduling and register allocation, and implemented it for compiler optimization in a machine description in a trimaran infrastructure for exploitation of instruction-level parallelism. For this experimental work, the authors added machine descriptions (MDES) targeted to HL-PD architecture. As a result, only a few spills were needed and the quality of the code generated was improved. The application of abstract base graph has been applied for experimental purposes. For these experiments, this article used 20 benchmarks available with trimaran infrastructure for HPL-PD architecture. This article compares some of these results with results obtained performed on LLVM compiler on an MIPS architecture. The implemented algorithm is based on subgraph isomorphism. The input program is represented in the form of directed acyclic graph (DAG). The vertices of the DAG represent the instructions, input, and output operands of the program, while the edges represent dependencies among the instructions.