Abstract
A compact VLSI MOSFET model that includes an integrated thermal noise model and a methodology for the analysis of the effects of thermal noise on the performance and error rates of digital integrated circuits is presented. The usefulness of the model and methodology is demonstrated by comparing simulation results for signal-to-noise ratio to analytic results for the balanced bit-line architecture of the single-device DRAM and the associated cross-coupled pair sense amplifier. The design options and tradeoffs related to thermal noise are introduced for both the balanced bit lines and the sense amplifier are considered. The error rate as a function of signal-to-noise ratio is determined, and possible limits to DRAM construction due to inherent thermal noise are highlighted. >
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