A Compact Quasi-Static Terminal Charge and Drain Current Model for Double-Gate Junctionless Transistors and Its Circuit Validation

Abstract

Junctionless transistors (JLTs) are presumed more scalable compared to other technologies, but its circuit performance is not fully understood. In this paper, we develop a charge-based compact model for a double-gate JLT(DGJLT) to explore the dc and the quasi-static performance of the transistor technology. First, 1-D Poisson’s equation is solved analytically by using the Lambert function to obtain the (sheet) charge density in the channel. Second, a continuous charge-based drain current model is derived for long-channel DGJLTs using the Pao-Sah’s dual integral. The model applies to all working regions (i.e., fully depleted, partly depleted, and accumulation). Third, based on the drain current, we develop the terminal charge model for ac and transient circuit simulation. Finally, the short-channel effect is modeled by adding an effective gate voltage to the proposed long-channel model. The compact model is validated by a numerical simulator over a wide range of voltage bias and device geometries. Results predicted by the analytical model agree well with numerical results. The model has been implemented in the Hspice circuit simulator with Verilog-A language and used to simulate a DGJLT inverter and oscillator without any convergence problem.