Abstract
AbstractAn innovative design methodology is presented to simplify the architecture of outphasing power amplifier (PA). The proposed design, by absorbing transistor parasitic capacitance into reactance compensating network intrinsic for a Chireix outphasing amplifier, greatly reduces the complexity of impedance modulation network at the output side, hence reducing the overall circuit size. Theoretical formulations regarding the introduced design technique are fully described and the effectiveness is verified through the implementation of a 2.6‐GHz PA prototype intended for long term evolution application. The realized circuit achieves maximum power of 44.8 dBm based on two 10‐W gallium nitride (GaN) high electron mobility transistor (HEMTs), accompanying maximum 73.3% drain efficiency between the saturation point and 6‐dB output back‐off point. At the 6‐dB output back‐off point, the drain efficiency reaches 63.5%.
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