A compact neural network for VLSI PRML detectors: scalable architecture

Abstract

Very large scale integration (VLSI) compact neural network architecture for maximum-likelihood detector of partial response (PR) communication receivers is presented. The compact neural network approach has many attractive advantages in achieving low power, low cost, compact chip area, and faster processing speed by its loosely coupled parallel processing nature. In this paper, the design of a state-constrained analog neural processor, and the corresponding parallel architecture to realize the PR detection algorithms and the related scalability and performance evaluation issues are described with detailed design analysis. A design example of a PR IV detector has been used to demonstrate the advantages of such a scalable massive VLSI architecture. A processing rate of 265 Mb/s was achieved with SPICE simulation for a prototype PR IV detector on a silicon area of 5.14 mm/spl times/5.81 mm in a 1.2 /spl mu/m CMOS technology. An estimated processing capacity of 886 Mb/s can be achieved if the same design is scaled up to a 1.0 cm/sup 2/ silicon area for the same technology. Such promising performance potential clearly indicates that VLSI compact neural network detector can meet the needs in future high speed data communication systems at very low cost.