Abstract
This paper presents a compact low-jitter phase-locked loop (PLL) for high-frequency clock generation to be integrated in the front-end electronic readout of high energy physics experiments. The PLL is based on a LC voltage-controlled oscillator with a tuning range between 4.8 and 6 GHz. The PLL features a jitter below 4-ps rms with a power consumption of 18 mW. It has been designed in a CMOS 65-nm technology and occupies a silicon area of just 0.124 mm2. Irradiation tests showed that the design is still fully functional after a total dose of 2.5 MGy, with a moderate jitter increase.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
