A compact, high-gain Q-band stacked power amplifier in 45nm SOI CMOS with 19.2dBm P<sub>sat</sub> and 19% PAE

Abstract

We present a compact, high-gain power amplifier (PA) that achieves high power and high output impedance through a 4-stacked architecture. By proper adjustment of device sizes and bias voltages, the optimum load impedance for maximum Psat is moved close to 50Ohm which eliminates the need for an output matching network. The single-stage PA exhibits a high gain of 16 dB which is more than twice the gain of previously reported PAs and 19.2dBm Psat and 19% PAE which are comparable to the state-of-the-art CMOS PAs at Q-band. The very compact area of 0.09 mm2 and the high gain makes this design a suitable unit PA to be used for further parallel power combining to reach Watt levels of output power.